1. Field of the Invention
The present invention relates to a semiconductor device such as an IGBT (insulated gate bipolar transistor) and a method of fabricating the same.
2. Description of the Background Art
Increase in performance of semiconductor devices essentially necessitates size reduction thereof, and the same is true for power semiconductor devices without exception. However, the further size reduction of the semiconductor devices has caused the surface of the semiconductor devices to be of more uneven configuration per unit area and has adversely affected element performance, fabrication steps, and reliability. For power semiconductor devices such as power transistors, power MOSFETs, IGBTs, thyristors, GTOs, MOS gate thyristors which have a current density ranging from several to make hundreds of amperes per square centimeter, in particular, high-priority challenges are: (1) to increase the thickness of surface aluminum electrode wiring; (2) to uniform the first thickness thereof; and (3) to flatten the surface aluminum electrode wiring.
Achievement of the second challenge (1) decreases the resistance of the aluminum electrode wiring to reduce power loss and increases the operating frequency of the device. Achievement of the third challenge (2) provides uniform resistances in the aluminum electrode wiring to allow safe operation of the whole device and expansion of a safe operating area (SOA). Achievement of the challenge (3) decreases contact resistances in wire bonding and pressure contact during package assembly for semiconductor chips.
Recently, with increasing integration and performance of general semiconductor devices, circuit patterns in the devices have been smaller in size and have been required to be formed with high accuracy.
On the other hand, the circuit patterns of power semiconductor devices were not much smaller than those of other semiconductor devices. In recent years, however, there has been an increasing tendency toward size reduction of the circuit patterns of power semiconductor devices for high integration and high performance, like the general semiconductor devices.
In the power semiconductor devices, a large number of process steps prior to the process step of forming electrode wiring for connection between electrodes or between an electrode and an external terminal often resulted in a surface configuration having high stepped portions before the formation of the electrode wiring.
Aluminum or an aluminum alloy such as AlSi is generally used for electrode wiring. It is, however, technically difficult to flatten Al or Al alloys, and improvements therein have been desired.
FIG. 28 is a schematic sectional view of a trench gate type IGBT (insulated gate bipolar transistor) which is a conventional power semiconductor device having a high stepped pattern in the electrode wiring.
Formation of electrode wiring in the conventional trench gate type IGBT will be described, as an example, with reference to FIG. 28.
As shown in FIG. 28, a p.sup.+ semiconductor substrate 1 has first and second major surfaces, and an n.sup.- semiconductor layer 2 is formed on the first major surface of the p.sup.+ semiconductor substrate 1. A p semiconductor layer 3 is formed on the n.sup.- semiconductor layer 2, and an n.sup.+ semiconductor layer 4 is formed on the p semiconductor layer 3. A plurality of trenches 13 (two trenches in FIG. 28) are formed extending from the surface of the n.sup.+ semiconductor layer 4 through the n.sup.+ semiconductor layer 4 and p semiconductor layer 3 into parts of the surface of the n.sup.- semiconductor layer 2. The trenches 13 are of a Y-shaped cross-sectional configuration with a rounded bottom.
A silicon oxide film 14 is formed in the trenches 13 as a gate insulating film, and most of the inner region of each trench 13 is filled with doped polysilicon 5 which is a low-resistance conductive filler material, with the silicon oxide film 14 sandwiched between the doped polysilicon 5 and the inner wall of each trench 13. An example of the doped polysilicon 5 includes phosphorus-doped n-type polysilicon. The doped polysilicon 5 functions as a control electrode, and regions of the p semiconductor layer 3 adjacent the opposite outer wall surfaces of the trenches 13 serve as channel regions.
Silicon oxide films 7 are formed on the polysilicon 5, for example, in the manner to be described below. After the doped polysilicon 5, entirely filled in the trenches 13, is etched in some amounts in the direction of the depth of the trenches 13, the silicon oxide films 7 are formed on the doped polysilicon 5 by means of the CVD technique for the purpose of covering the openings of the trenches 13. The silicon oxide fihns 7 cap the openings of the trenches 13.
A high melting point metal film 8 serving as a silicide layer for low ohmic resistances or a barrier metal is deposited over the silicon oxide films 7, and an electrode wiring layer 6 made of an Al alloy is formed over the high melting point metal film 8. In this case, the high melting point metal film 8 is an alloy film.
In the conventional trench gate type IGBT as above constructed, a cavity or hollow 9 is produced in the electrode wiring layer 6 by reflecting the shape of the sharp tips of the silicon oxide films 7 on the doped polysilicon 5 in the trenches 13. The cavity or hollow in the electrode wiring layer 6 increases electrical resistances of the electrode wiring layer 6 which in turn fails to provide desired electrical characteristics.
In extreme cases, the cavity or hollow causes the electrode wiring layer 6 to be disconnected in the high stepped portions, resulting in fatal defects in terms of electrical resistances and reliability.